Computer Memory and Variables'-Addressing Concepts
Computer memory system is how a computer stores and retrieves data for processing.
Let's understand more with the help of a Table below:
| Level | Name | Speed | Size | Volatility | Purpose |
|---|---|---|---|---|---|
| 0 | CPU-Registers | ~1 cycle | ~KB | Volatile | Hold data for current instruction |
| 1 | L1/L2/L3 Cache | ~3-30 cycles | ~MB | Volatile | Hold hot data to avoid RAM trips |
| 2 | Main Memory RAM | ~100 cycles | ~GB | Volatile | Running programs, OS, stack, heap |
| 3 | SSD / HDD | ~100,000 cycles | ~TB | Non-volatile | Files, apps, OS on disk |
| 4 | Cloud / Tape | seconds+ | ~PB | Non-volatile | Backup, archive |
How data flows: CPU asks for data → checks L1 cache → L2 → L3 → RAM → SSD. Each level is bigger + slower. This is called "locality-of-reference": programs tend to reuse nearby data/code, so caching works.
Memory-Management by OS:
Key idea: "Memory wall" = CPU is much faster than RAM. So we use caching + hierarchy to hide latency.
Addressing modes - how instructions specify addresses:
- Immediate: MOV AX, 5 → value is part of instruction
- Direct: MOV AX, [1000] → use address 1000 directly
- Indirect: MOV AX, [BX] → address is in register BX
- Indexed: MOV AX, [BX + SI] → base + offset
- Relative: JMP +10 → address relative to current PC
Addressing answers: "Where exactly is this byte?"
Physical vs Virtual Addressing:
Why virtual? 3 big benefits:
Memory-Mapping-Techniques:
So in short: Memory hierarchy gives speed vs capacity tradeoff, and addressing gives us a way for programs to safely and efficiently access that memory without knowing physical layout.
Addressing Modes in CPU instructions
CPU has to encode "where to get data" in the instruction itself. Common modes:
Paging vs Segmentation
Multi-level Page Tables
For 64-bit systems, 2^64 addresses is too big for 1 table. So OS uses 4-level page tables:
Virtual address = 9 bits Level4 + 9 bits Level3 + 9 bits Level2 + 9 bits Level1 + 12 bits offset.
This is why malloc doesn’t crash even though your program "has" 128TB of address space.
Real-world example: Android-Application
Your Android app runs in its own virtual address space. When you read a file, kernel maps SSD page to RAM page, then maps RAM page to your app’s virtual address. If you access unmapped memory, you get SIGSEGV = crash.
So: Memory hierarchy = performance. Addressing = abstraction + protection.
Now, you all knew about cache-memories and we see how it works inside the computer-system.
Cache Lines & Cache Misses
Central Processing Unit doesn’t fetch 1 byte from RAM at a time. It fetches in chunks called cache-lines, usually 64 bytes on modern x86/ARM.
How it works:
Types of cache misses:
Code impact example:
"for(i=0; i<1000; i++)
for(j=0; j<1000; j++)
sum += arr[i][j]; // row-major = cache friendly
This is fast because arr[i][j] and arr[i][j+1] are in same cache line.
for(j=0; j<1000; j++)
for(i=0; i<1000; i++)
sum += arr[i][j]; // column-major = cache unfriendly
This jumps 4000 bytes each step, causes tons of cache misses."
Virtual Memory: Mobile vs Desktop
Both use paging, but constraints are different:
Desktop / Server:
Mobile / Android:
Real-impact:
Putting it together: Why this matters for developers?
So memory hierarchy gives speed, addressing gives safety, and understanding both helps you write code that runs fast on both Personal-Computer and Mobile-Device.
Virtual → Physical Address Lookup - Simple version:
Your program asks for 0x7ffd1234 = Virtual Address
CPU splits it: Page Number + Offset
Page Table = map that page number to a physical RAM frame
Physical Address = Frame Number + Offset → actual RAM chip
If page not in RAM = Page Fault → OS loads it from SSD
A virtual address is a binary, logical address generated by a CPU or program that acts as a reference to a memory location, independent of the computer's actual physical RAM. It provides an abstraction layer, allowing programs to operate within their own isolated "virtual address space".
Key Characteristics and Concepts:
This system enables efficient memory management and allows modern operating systems to run applications that require more memory than is physically installed.
A virtual address in hexadecimal is a base-16 memory identifier (e.g., 0x7ffd1234) used by applications, which the Operating System's Memory Management Unit (MMU) translates into physical RAM locations. Hexadecimal is used to compactly represent binary addresses, where 4 bits map directly to one hex digit (0-F).
A virtual address is a binary address assigned by the operating system to a process, representing a memory location in "virtual memory" rather than physical RAM. It provides an abstract, consistent memory view for programs, which is translated to actual physical locations by the memory management unit (MMU).
Key Aspects of Virtual Addresses:
Virtual vs. Physical Addresses
Key Aspects of Virtual Addresses (Hexadecimal)
0x followed by alphanumeric characters, making long binary strings (e.g., 32-bit or 64-bit) readable for developers and systems.0x7F3E5234 is often split into a virtual page number and a page offset.0x00000000 to 0xFFFFFFFF.0x7FFF'FFFFFFFF.0x0012F980 is broken down by the Memory Managemengt Unit (e.g., lower 12 bits 0x980 as offset) and mapped to a physical address (e.g., 0x0012F980).Why Hexadecimal is Used
0x4000 is easier to read and debug than 0100000000000000.The offset in a virtual address represents the specific location of data within a memory page, typically identified by the lower bits of the virtual address. In a standard {4 KB (2^12) bytes} page system, the offset is 12 bits, corresponding to the last 3 hexadecimal digits (e.g., 0x000 to 0xFFF). It defines the distance from the start of the page, remaining constant during translation.
Key Aspects of Virtual Address Offsets
0x7F3E5234234) represent the offset.virtual_address & 0xFFF".Example of Hexadecimal Offset
Given a 32-bit virtual address 0x7F3E5234:
0111 1111 0011 1110 0101 0010 0011 01000111 1111 0011 1110 0101 (page #) | 0010 0011 0100 (offset)0x234 In this scenario, 0x234 is the position within that specific (4 KB) page.
In computer science, "0x" is a prefix used to indicate that the following number is written in hexadecimal (base-16) notation. It has no numerical value on its own and is purely a visual label for compilers, interpreters, and programmers.
Why "0x" Is Used?
10 means ten, but 0x10 means sixteen.0 signals the compiler that a numeric literal is starting, and the x stands for "hexadecimal."Comparative Examples
| Representation | Value as Decimal | Meaning |
|---|---|---|
15 |
15 | Standard decimal fifteen |
0x15 |
21 | Hexadecimal (1 *16 + 5) |
0x234 |
564 | The offset from the previous example (2 * 256 + 3 * 16 + 4) |
0xFFF |
4095 | The maximum offset in a 4 KB page |
In computer memory management, specifically paging, a logical (virtual) address generated by the CPU is divided into a page-number (p) and a page-offset (d). The page number serves as an index into a page table, identifying which specific page of a process is being accessed, while the offset provides the exact displacement or location within that page.
Core Analogy: Book Chapter and Sentence
To understand address translation without complex math, think of virtual memory like a book:
When the computer maps this to physical hardware, the "chapters" (pages) are shuffled and stored 'out-of-order' in physical memory "slots" (frames). However, the text inside the chapter remains exactly the same.
Therefore, the system only needs to translate the chapter number. Once it finds where Chapter 5 is physically stored, it counts down 12 sentences to get your data.
Key Components
Structure of a Logical Address
If the logical address space is 2m and the page size is 2n, the address is divided as follows:
TEXT
|-------------------|-------------------|
| Page Number (p) | Page Offset (d) |
|-------------------|-------------------|
Example Calculation
If a system has a 16-bit logical address and a page size of 4 KB [Kilo-{4096 = 212 bytes}-Bytes]:
0000 0000 0000 0000 (binary) <---> We're dealing with Hexa-Decimal Numbers;0000 (First 4 bits)0000 0000 0000 (Last 12 bits)Address Translation Process
Step-by-Step Translation Mechanism
When a program requests data at a specific logical address, the Hardware Memory Management Unit (MMU) performs the following physical translation:
Logical Address Generated by CPU
+-------------------+-------------------+
| Page Number (p) | Page Offset (d) |
+---------+---------+---------+---------+
| |
v |
[ PAGE TABLE ] |
| p -> Frame# | |
+------+-------+ |
| |
v v
+-------------------+-------------------+
| Frame Number (f) | Page Offset (d) |
+-------------------+-------------------+
Physical Address Location in RAM
Why the Offset Never Changes
A common point of confusion is why the offset remains identical in both virtual and physical addresses.
Bit-Level Breakdown Example
To see how the hardware splits these numbers instantly, look at a 16-bit system using small 256-byte pages:
If a CPU requests binary address 00000100 00001111 (Decimal 1039):
00000100 (The first 8 bits = Page 4)00001111 (The last 8 bits = Offset 15)The operating system checks the Page Table and finds that Page 4 is currently residing in physical RAM Frame 30 (00011110 in binary).
The MMU replaces the page bits with the frame bits, keeping the offset untouched:
00011110 00001111 (Frame 30, Offset 15).In computer memory management, physical frames (or page frames) are fixed-size, contiguous blocks of physical hardware memory (RAM).
While virtual memory is divided into pages, the physical RAM chip is divided into frames. For the system to function correctly, a physical frame must be the exact same size as a virtual page.
The Dynamic Mapping Relationship
Physical frames act as physical slots or containers that hold virtual pages.
Key Attributes of Physical Frames
Frame Allocation and the Page Table
The Page Table is the master map kept by the operating system to keep track of which virtual page is currently sitting inside which physical frame.
| Virtual Page Number | Valid/Invalid Bit | Physical Frame Number (PFN) |
|---|---|---|
| Page 0 | 1 (In RAM) | Frame 5 |
| Page 1 | 0 (On Disk / Swap) | — (None) |
| Page 2 | 1 (In RAM) | Frame 12 |
Frame Management and Thrashing
Because physical RAM is limited, a computer usually has far fewer physical frames than the total number of virtual pages requested by running programs.
In computer memory management, a page table is the master data structure maintained by the operating system to map a process's virtual page numbers to physical frame numbers in RAM.
Every running process has its own dedicated page table. Without it, the processor's Memory Management Unit (MMU) cannot translate virtual memory addresses into physical hardware addresses to retrieve data.
The Translation Lookup Process
When a program requests a specific memory address, the hardware intercepts the request and reads the page table: [1]
Virtual Address: [ Page Number (p) | Offset (d) ]
|
v
+------------------+
Page Table -> | Index p: Frame f |
+------------------+
|
v
Physical Address: [ Frame Number (f) | Offset (d) ]
Inside a Page Table Entry (PTE)
A page table does not just store frame numbers. Each row, known as a Page Table Entry (PTE), contains several critical control bits used by the hardware and operating system:
Modern Page Table Architectures
Storing a massive, flat array for every single process consumes too much physical RAM. Modern operating systems use optimized structural layouts to keep page tables compact:
Hierarchical (Hierarchical / Multi-level) Page Tables: This method breaks the virtual address into multiple page numbers, splitting the master table into a tree structure of smaller tables. If a large block of memory is unused, its sub-tables do not need to exist in RAM, saving massive amounts of space.
Inverted Page Tables: Instead of creating a table for every process's virtual space, the system maintains one single table for the entire physical RAM. It contains exactly one entry for each physical frame, tracking which process and page currently occupy that hardware slot.
Translation Lookaside Buffer (TLB) Cache: Because checking a page-table in RAM adds an extra hardware memory access delay, CPUs use a specialized, ultra-fast hardware cache called the TLB. The TLB stores the most recently used page-to-frame translations, allowing the MMU to skip the page table lookup entirely for the vast majority of memory requests.
To see exactly how Page Numbers, Page Offsets, Physical Frames, and Page Tables work together in real life, let us walk through a concrete example step-by-step.
The Scenario
Imagine a 16-bit computer where a program wants to execute a command located at Logical Address 92.
Step 1: The CPU Splits the Address
The program asks for Address 92. In binary, 92 is written as a 16-bit number: 00000000 01011100.
The hardware immediately splits this binary string into two parts based on our 5-bit offset rule:
| Page-Number(p) | Page-Offset(d) |
00000000111(First '11' Bits) |
11100(Last '5' Bits) |
| Decimal-2 | Decimal-28 |
The computer now knows it needs Page 2, and specifically Byte number 28 inside that page.
Step 2: The Memory Management Unit Checks the Page Table
The CPU cannot go directly to the physical RAM chip yet because RAM does not know what "Page 2" means. The hardware looks at the running process's Page Table to see where Page 2 is currently sitting in the actual physical RAM slots (Frames):
| Index (Page Number) | Valid Bit | Physical Frame Number |
|---|---|---|
| Page 0 | 1 | Frame 5 |
| Page 1 | 1 | Frame 9 |
| Page 2 | 1 | Frame 7 |
| Page 3 | 0 | — (On Hard Drive) |
The hardware looks up index 2, sees a Valid Bit of 1 (it is loaded in RAM), and pulls out the target: Physical Frame 7.
Step 3: Constructing the Physical Address
To pinpoint the exact location on the hardware RAM chip, the Memory Management Unit combines the Frame Number (7) with the unaltered Offset (28).
00000000111.11100.Physical Address = [Frame 7 | Frame 28] --> 0000000011111100
Converting 0000000011111100 back to a regular number gives Physical RAM Address 252.
Final Summary of the Journey
[ Program asks for Address 92 ]
|
v
[ Page 2, Offset 28 ]
|
(Look up in Page Table)
|
v
[ Frame 7, Offset 28 ]
|
v
[ Hardware fetches RAM Address 252 ]
Because Page 7 starts at byte 224 (7*32), counting 28 bytes into Frame 7 lands exactly on physical address 252. The translation is complete, and the data is fed back to the CPU.
What Happens When Things Go Wrong: A Page Fault
Let’s use the exact same scenario from before, but this time, the CPU asks for Logical Address 100.
When the computer splits the address, it discovers this data is located on Page 3, Offset 4. It goes to check the Page Table:
| Index (Page Number) | Valid Bit | Physical Frame Number |
|---|---|---|
| ... | ... | ... |
| Page 3 | 0 | — (Not in RAM) |
Because the Valid Bit is 0, the data is not in the physical RAM frames; it is sitting on the slow storage drive (SSD/HDD). This triggers a hardware interruption called a Page Fault.
Step-by-Step Page Fault Resolution
[ CPU Requests Page 3 ] -> [ Valid Bit is 0 ] -> [ PAGE FAULT! ]
|
+----------------------------------------------------+
v
1. OS Traps the error and pauses the program.
2. OS finds an empty physical frame in RAM (e.g., Frame 12).
3. OS reads Page 3 from the storage drive and copies it into Frame 12.
4. OS updates Page Table: Page 3 -> Frame 12 (Valid Bit changes to 1).
5. OS restarts the program instruction.
|
v
[ Data successfully fetched from Frame 12! ]
Grand Summary: Bringing It All Together
To wrap up everything we have discussed, here is the complete reference cheat sheet of how memory management operates: